This invention relates to semiconductor devices, and more particularly to semiconductor devices with magnetic material layers.
Semiconductor devices are used in many electronic applications. Semiconductor devices are made by depositing, patterning and etching one or more conductive, insulating and semiconductive layers on a semiconductor wafer. Semiconductor devices may include analog or digital circuits, memory devices, logic circuits, or combinations thereof, as examples.
A more recent development in semiconductor memory devices are resistive memory devices, which use magnetics to store a bit of information, rather than storing a charge, as in prior art memory devices such as Dynamic Random Access Memory (DRAM) devices. Magnetic materials are used in the manufacture of resistive memory devices. One such resistive memory device is a Magnetic Random Access Memory (MRAM) device, which is increasing in popularity as a storage device because of its advantages of non-volatility, three dimensional cell packing capability, lower power consumption, and simpler and less expensive processing compared to conventional DRAM devices and nonvolatile flash memories, as examples.
MRAM devices use the relative orientation of the magnetization in ferromagnetic materials to store information. Digital information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is storable in the alignment of magnetic moments. The resistance of the magnetic component depends on the moment""s alignment. The stored state is read from the memory element by detecting the component""s resistive state. A memory cell may be constructed by placing conductive lines in a matrix structure having rows and columns, with the memory cells being disposed at the cross-points of the conductive lines.
Manufacturing MRAMs is challenging and presents a different set of problems than conventional memory devices. For example, multiple layers of magnetic materials are used, which often comprise iron and other easily corroded materials. Magnetic material layers may be negatively affected by surface irregularities of underlying layers, which can be problematic in semiconductor processing and may cause Neel coupling.
Also, in the manufacturing of MRAMs, copper is frequently used as the conductive line material to access e.g., read and write information to the magnetic storage cells. Copper corrodes easily and may diffuse into adjacent insulating layers, causing device failures. Because copper is difficult to etch, copper conductive lines are usually formed using a damascene process, in which holes and trenches are formed within a dielectric, and then filled with a conductor. A subsequent Chemical-Mechanical Polishing (CMP) step removes excess copper from the top surface of the dielectric.
When a conventional CMP process is used, the edges of patterned features such as conductive lines 16 tend to have additional edge topography 11, as shown on the substrate 10 in FIG. 1. The edge topography 11 may include protrusions or recesses that extend above or below the conductive line 16 surface, which are caused by erosion and dishing. The conductive lines 16 may include a metallic liner, for example. This edge topography 11 may adversely impact device performance, particularly with MRAM devices. The defects 11 in the edge topography create a surface irregularity, and may distort or cause pinning effects on the magnetic field of the domains of overlying ferromagnetic materials. Distortion and pinning results in undesirable magnetostatic fields. Also, additional edge topography 11 may introduce shorts through the thin magnetic tunneling junction when the magnetic stack is deposited over the edge topography.
Another problem in manufacturing MRAMs is the possibility of overetching the magnetic stack material, which may cause damage to the underlying conductive layer. In order for the MRAM device to function properly, the magnetic stack material is typically required to be adjacent to, or electrically coupled to the underlying conductive line, which may comprise a wordline or bitline of the array, for example. Etching the magnetic stack layer while stopping on the interconnect layer, without corroding or re-sputtering the interconnect metal onto the magnetic stack, is a challenge.
Embodiments of the present invention achieve technical advantages as a structure and method for preventing problems with the magnetic material stack to underlying conductive line material interface. An insulating cap layer and a conductive cap layer are utilized to prevent a direct interface with the magnetic material stack to the underlying conductive line material. The insulating cap layer is deposited over the conductive lines before the magnetic stack deposition. The insulating cap layer functions as a etch stop when etching the magnetic stack.
In one embodiment, a method of fabricating a semiconductor device includes providing a substrate, depositing a dielectric material over the substrate, and forming a plurality of first conductive lines within the dielectric material. An insulating cap layer is deposited over the first conductive lines and the dielectric material, the insulating cap layer is patterned, and portions of the insulating cap layer are removed from over stack portions of the first conductive lines. A magnetic stack material is deposited over the insulating cap layer.
In another embodiment, a semiconductor device includes a substrate, a dielectric material formed over the substrate, and a plurality of first conductive lines formed within the dielectric material. The first conductive lines include stack portions and non-stack portions. An insulating cap layer is disposed over at least the first conductive line non-stack portions. A magnetic material stack is disposed over each first conductive line stack portion.
Advantages of embodiments of the invention include protecting the underlying first conductive lines with the insulating cap layer during the magnetic stack etch process, preventing corroding or sputtering of the first conductive line material during the magnetic stack etch. Advantageously, the insulating cap layer is adapted to function as an etch stop for the magnetic stack etch. The use of a conductive cap layer over the conductive lines ensures that the magnetic memory cells are formed over a texturally smooth surface, reducing or eliminating Neel coupling effects, minimizing surface topography, and improving MRAM device reliability and performance.